This invention relates to semiconductor chip packaging, and, more particularly, to a method and structure for providing improved diamond thermal conduction structures for semiconductor devices.
As the silicon chip technology drives for speed, density and integration, the power dissipation problems can significantly limit the system performance and reliability and the chip sizes. In addition, thermal management for effective heat removal and temperature equalization becomes more challenging as density and integration demands increase. Semiconductor chips require cooling to sustain reliability of circuits and interconnects formed on and in the semiconductor chips, to optimize circuit switching performance, and to suppress thermally generated noise in the circuits.
Although is has been demonstrated that, by placing processor and peripheral chips, such as cache memory, directory and multimedia chips in the same package, one can greatly improve the speed, bandwidth and power reductions, the attendant temperature increase induces performance degradation, reduction in reliability, and mechanical failure, greatly setting back the overall performance.
As a result, a myriad of cooling structures have been devised for incorporation into the semiconductor chip structure itself and for use in the mounting of semiconductor chips. Cooling may be provided for an entire circuit board, may be applied selectively to individual chips, or may be provided on-chip to dissipate heat from individual hot spots within a chip. An example of a prior art cooling solutions is U.S. Pat. No. 5,621,616 of A. H. Owens, wherein a high conductivity thermal transfer pathway is created, using multiple metal layers and vias, to draw heat away from the bulk silicon semiconductor substrate. Owens additionally proposes embedding metal plugs into a chip substrate to collect heat generated by transistors and remove the heat through metal interconnects in the chips.
Yet another proposed solution is found in U. S. patent application Ser. No. 09/006,575, of Joshi, et al, entitled xe2x80x9cEmbedded Thermal Conductors for Semiconductor Chipsxe2x80x9d, filed on Jan. 13, 1998 and currently under allowance, and its divisional case Ser. No. 09/296,846 filed Apr. 22, 1999, both of which are assigned to the present assignee. In accordance with the teachings of those applications, the contents of which are incorporated by reference herein, back-side diamond thermal paths are provided effectively to act as cooling fins; or alternatively, front-side shallow trench diamond thermal conductors are provided in contact with the devices at the substrate surface and extend through the buried oxide layer to contact the underlying bulk silicon. The shallow trench diamond structures provide both electrical isolation between devices and thermal conduction of heat away from the devices. A disadvantage to the former Joshi structure is that back-side cooling does nothing for dissipating heat away from the front-side-mounted devices. A disadvantage to the latter Joshi front-side structure and method is that the trenches are formed prior to device fabrication. As a result, the diamond in the trenches must be recessed and covered to protect it from the subsequent processing steps; thereby requiring numerous additional processing steps and resulting in an unusual structural profile.
It is therefore an objective of the present invention to provide improved cooling of semiconductor chips.
It is additionally an objective of the invention to provide a chip package which provides enhanced thermal cooling of the chips mounted thereon.
Yet another objective of the invention is to provide an alternative chip mounting structure which provides improved heat dissipation.
These and other objectives are realized by the present invention including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.